1. Field of the Invention
This invention relates to Phase Locked Loop (PLL) circuits and more specifically to phase align detection circuits in a multi-clock domain.
2. Description of the Related Art
Generally, PLLs are used to generate multiple clock frequencies from a reference clock in a system. PLLs synthesize multiple clocks in a predefined frequency relationship to the reference clock frequency in the same clock domain. However, in a system with multiple clock domains, when signals cross clock domain then due to jitters and errors generated by PLLs in each clock domain, it is difficult to determine clocks' alignment even when the clocks are derived from a single reference.
An apparatus and method is needed to determine the alignment of clocks in multiple clock domains system.